The present invention relates to a nonvolatile semiconductor memory device of a two-layered gate structure, such as a flash EEPROM and a method for manufacturing the same.
In recent years, a NAND cell type EEPROM has been proposed as one of electrically erasable semiconductor memory devices. This NAND cell type EEPROM is of such a type that a plurality of memory cells are provided with their source and drain shared by adjacent ones in a series-connected manner and each cell connected as one unit to a corresponding bit line. The respective memory cell constitutes a two-layered gate structure with a floating gate (charge storage layer) and control gate stacked with an insulating film therebetween.
In this type of nonvolatile semiconductor memory device, a shallow trench isolation (STI) is adopted, as an element isolation area, in place of a LOCOS (Local oxidation of silicon). In the case where a nonvolatile semiconductor memory device using such an STI is manufactured, a process for forming a floating gate is used before forming a trench.
FIGS. 7 and 8 show a conventional nonvolatile semiconductor memory device using a process for forming a floating gate in advance.
In FIGS. 7 and 8, a gate oxide film 102 and plurality of floating gates 103 of, for example, polysilicon are formed over a surface of a semiconductor substrate 101. A buried insulating film 104 of, for example, a silicon oxide film constituting an STI area is formed in a semiconductor substrate 101 at an area situated between those floating gates 103. For example, an ONO film 105 is formed as a composite insulating film on the respective floating gate 103. A control gate 106 of, for example, polysilicon is formed on the ONO film 105. A mask material 107 of, for example, silicon nitride film is formed on the control gate 106. The mask material 107 is used as a mask when the control gate 106 and floating gate 103 are etched.
As shown in FIG. 7, the floating gate 103 is comprised of a first floating gate 103a and second floating gate 103b formed on the first floating gate 103a. The buried insulating film 104 is formed after the formation of the first floating gate 103a but before the formation of the second floating gate 103b. 
That is, the gate oxide film 102, first floating gate 103a of, for example, polysilicon and mask material (not shown) of, for example, a silicon nitride film are sequentially formed over the surface of a semiconductor substrate 101. The mask material is subjected to a patterning process. With the patterned mask material used as a mask, the first floating gate 103a, gate oxide film 102 and semiconductor substrate 101 are dry etched, for example, are reactive ion etched (RIE) to provide a plurality of trenches 108.
Then, a silicon oxide film is deposited, by a chemical vapor deposition (CVD) method, on a whole surface and, by doing so, the trench is buried with the silicon oxide film. Thereafter, with the mask material used as a stopper, the silicon oxide film is planarized by a chemical mechanical polishing (CMP) method to provide the buried insulating film 104. Then the second floating gate 103b is formed on the first floating gate 103a. 
In the case where the floating gate is initially formed as set out above, the floating gate 103 is comprised of the first floating gate 103a and second floating gate 103b and hence is made thicker. As shown in FIG. 8, therefore, when the floating gate 103 is etched back to the gate oxide film 102 with the mask material 107 and control gate 106 as a mask, the aspect ratio becomes greater. It is, therefore, difficult to set a selection ratio between the polysilicon as the floating gate 103 and the gate oxide film optimal. In the case where, for example, the selection ratio is set greater, the polysilicon is less likely to be etched. This provides a possibility of the polysilicon remaining. In the case where, on the other hand, the selection ratio is set smaller, etching is not stopped to the gate oxide film 102 and reaches the semiconductor substrate 101, thus presenting a problem.